FirstEDA provide high-quality instructor-led training in languages and methodologies, as well as tool proficiency. Our courses and workshops are developed and delivered by our own highly experienced engineers or through our long-standing partnership with industry-renowned VHDL specialist Jim Lewis, of SynthWorks, who actively contributes to IEEE VHDL standards and the Open Source VHDL Verification Methodology (OSVVM).


Our engineering experiences, past and present, add immense value to all of our courses and ensure the training you receive is fit-for-purpose. For instance, we can teach you best-practice coding techniques and guide you on how to formalise your verification processes; all of which helps reduce project timeframes.

Our VHDL training courses are engaging, practical and sociable, and we certainly haven’t lost sight of the fact that engineering is both interesting and rewarding. Whether attending to learn new skills or to enhance your current ones, you will be mixing with like-minded individuals, all of whom are keen to learn new techniques and methodologies that will further their careers.

Why choose FirstEDA?

  • Our courses are taught by time-served engineers with over 60 years combined experience in the industry
  • We can bring the training to you, and tweak course content to meet any specific requirements you may have
  • Our courses are cost effective and are highly reviewed


“The importance of keeping your engineering skills current and learning appropriate methodologies cannot be over-emphasised. Having worked with FirstEDA for a number of years now I have seen hundreds of engineers complete our courses and return to their organisations enlightened and enthused.”Jim Lewis, SynthWorks.


VHDL is a hardware description language (HDL) used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays (FPGA) and integrated circuits (IC). VHDL is an abbreviation of VHSIC (very high speed integrated circuit) Hardware Description Language.

The most recent Wilson Research Group ASIC and FPGA Functional Verification Study shows that over 60% of worldwide FPGA design is in VHDL. In Europe this figure is higher still. VHDL is a deterministic, highly self checking language and is therefore the preferred HDL for Avionics and Milaero, and for anyone designing safety critical and high reliability systems. VHDL is also the most up to date HDL available, and can be used for both design and verification, without the need to switch to confusing object oriented techniques for verification.

As a European company supporting European customers, we are committed to VHDL. We offer three Language & Methodology courses: VHDL for FPGA designers (which provides a thorough background in the writing, use and application of synthesisable VHDL); Intermediate VHDL (which pushes further into applications) and Advanced VHDL Testbenches & Verification (a.k.a. ‘OSVVM Boot Camp’ and the content of which includes transaction-level modelling, self-checking, functional coverage and constrained random test benches). All three courses include 50/50 lecture and lab time. 


Our Training Courses


VHDL for FPGA Designers - 2-Day Instructor-Led Training

Our introductory VHDL training course provides a thorough background in the use and application of synthesisable VHDL in digital hardware design. 

The training is structured around a set of basic component building blocks to demonstrate the application of VHDL.

This is the first part of our VHDL training series, covering basic concepts and syntax relating to the circuit structures covered, and gives the FPGA designer sufficient knowledge to start writing synthesisable VHDL upon successful completion of the course. We also provide additional VHDL training classes which cover the more advanced language constructs and methodologies.

Course benefits:

  • Provides a complete understanding of the basic concepts in VHDL
  • Introduces you to the syntax and language building blocks based on a number of common circuit elements
  • Gives you practical experience of writing and verifying simple VHDL designs


For full course details and dates, please see the course schedule.


Intermediate VHDL - 3-Day Instructor-Led Training

Ready for the next step? For those already familiar with VHDL (either through an introductory course or self-taught), this intermediate VHDL training course will broaden knowledge and enforce competency through application.

This instructor-led intermediate VHDL training was designed to bridge the gap between possessing a basic working knowledge of VHDL and our Advanced VHDL Verification & Testbenches course. All our courses are delivered by time-served engineers whose experiences go far beyond just the theory.

Course benefits:

  • Provides practical experience in writing, testing and synthesising VHDL code as well as how to implement it on an FPGA
  • Enhances your current understanding of VHDL through problematic hardware coding issues
  • Introduces you to transaction-based testbenches
  • Introduces FSM coding techniques
  • Provide VHDL hardware experience with an FPGA lab board

Each delegate will be provided with an FPGA development board which is used during the lab exercises and can be used after the course to further expand their VHDL knowledge.


For full course details and dates, please see the course schedule.


Advanced VHDL Testbenches & Verification - 3 or 5 Day Instructor-Led Training

Our Advanced VHDL training course teaches the latest VHDL Verification techniques and methodologies for FPGAs and ASICs, including the Open Source VHDL Verification Methodology (OSVVM).

You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).

Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.

Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM.

This training can either be delivered as a full 5-day course, or by attending two separate sessions, as detailed below:

Part 1: Essential VHDL Verification (3-day course)

You will learn to create structured transaction-based testbenches using either procedures or models (aka: verification IP or transaction level models). Both of these methods facilitate creation of simple, powerful, and readable tests.

Course benefits:

  • Use OSVVM’s structure transaction base framework
  • Write OSVVM Verification IP
  • Simplify test writing using interface transactions (CpuRead, CpuWrite)
  • Add error injection to interface transactions
  • Implement a test plan that maximises reuse from RTL to core to system-level tests
  • Write directed, algorithmic, constrained random, and Intelligent Coverage random tests
  • Write Functional Coverage to track your test requirements (test plan)
  • Simplify error reporting using OSVVM’s Alert and Affirm utilities
  • Simplify conditional message printing (such as for debug) using OSVVM’s log utilities
  • Add self-checking to tests
  • Use OSVVM’s Generic Scoreboards and FIFOs
  • Use OSVVM’s Synchronisation Utilities (WaitForBarrier, WaitForClock, …)
  • Model analogue values and periodic waveforms
  • Utilise OSVVM’s growing library of Open Source Verification IP


Part 2: Expert VHDL Verification (2-day course)

Building on the core topics covered in Essential VHDL Verification, Expert VHDL Verification teaches advanced topics including modeling multi-threaded models (such as AXI4-Lite), advanced functional coverage, advanced randomisation, creating data structures using protected types and access types, timing and execution, configurations and modeling RAM.

Course benefits:

  • Write complex, multi-threaded verification components, such as AXI-Lite
  • Use configurations to control which test runs
  • Validate self-checking models
  • Write AXI Stream Master and Slave Models
  • Write models with interrupt handling capability
  • Simplify memory model implementation using OSVVM’s MemoryPkg,
  • Write protected types and access types
  • Understand VHDL’s execution and timing
  • Advanced Coverage and Randomisation techniques


For full course details and dates, please see the course schedule.



For all of the above courses, delegates will be provided with high quality materials including a lecture book and a detailed lab book (supporting all of the material covered during the course). The courses are split roughly 50/50 between lecture and lab time, so there is plenty of opportunity to reinforce the theory.



Course Schedule

VHDL for FPGA Designers


This instructor-led training course provides a thorough background in the use and application of synthesisable VHDL in digital hardware design.

        Full Details/Reserve Your Place                         

09-10 Sep 2020


Intermediate VHDL


Ready for the next step? For those already familiar with VHDL (either through introductory training or self-taught), this course will broaden knowledge and enforce competency through application.


01-03 Apr 2020

09-11 Dec 2020

Essential VHDL Verification


Developed and delivered in person by VHDL specialist Jim Lewis, this is ideal for device (PLD/FPGA/ASIC) designers who are looking to improve their verification skills.


16-18 Mar 2020

1-3 Jun 2020

9-11 Nov 2020


Advanced VHDL Testbenches & Verification


Developed and delivered in person by VHDL specialist Jim Lewis, you will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment competitive with other verification languages, such as SystemVerilog (UVM). 

16-20 Mar 2020

1-5 June 2020

9-13 Nov 2020



Meet The Trainers

David Clift - Lead Trainer 

As well as developing and delivering our language and tool training, David is an Application Specialist at FirstEDA. David’s 30+ year electronics engineering career started at GEC Marconi 1984, where he worked as an electronics engineer before making the move to EDA in 1994. He has extensive experience in the development and use of HDL tools in both practical and training environments.
David’s widespread knowledge of the industry and it’s technology, languages and tools has enabled FirstEDA to deliver unique learning labs, with multiple tools to help meet your design challenges.


jim_small Jim Lewis - Training Partner, Verification & Methodology

Jim is the founder and Principal Trainer at US based VHDL training specialists, SynthWorks. Jim has thirty years of design teaching and problem solving experience. In addition, Jim is a seasoned ASIC and FPGA Design & Verifcation engineer, with many years of experience in custom model development and consulting. He is a founder of the Open Source VHDL Verifcation Methodology (OSVVM) and the principal architect of its packages and methodology. Jim is also chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and the VHDL standardisation efforts.