Sigasi Studio 4.6

Released 12-12-2019

Sigasi are proud to present the Sigasi Studio 4.6 release: A faster new (System)Verilog preprocessor, improved graphics, bug fixes and much more.

 

Editor improvements

Sigasi Studio 4.5 introduced a new, more responsive code editor. Thanks to feedback, Sigasi learned that in some scenarios the editor actually performed slower. This release improves those scenarios. Sigasi continue working on making Sigasi Studio the ideal HDL Development Environment for their users.

 

Verilog improvements

Sigasi have made some changes to how they handle include files and they made the preprocessor incremental.

 

(System)Verilog library mapping of include files

Starting with Sigasi Studio 4.6, Sigasi no longer add include (or 'header') files (*.vh, *.svh, *.h) to the build. In sigasi Studio 4.6, include files are only analysed if they are really included in a Verilog or SystemVerilog file. This change simplifies the project setup.

 

no_library_mapping_for_include_files

 

 

(System)Verilog preprocessor enhancements

Sigasi Studio 4.6 has a new, incremental preprocessing engine. During clean build this engine is 10x faster. For small code changes, the incremental approach leads to even higher speed improvements.

Sigasi also added more semantic highlighting in the preprocessor regions in your source files:

 

preprocessor_highlight

 

preprocessor_code_semantic_highlight

 

The autocomplete for preprocessor directives also received some extra love. It was tweaked to be more helpful in the most common use cases.

 

preprocessor_autocomplete

 

Because file encoding differences between including and included files can lead to unexpected, very difficult to find bugs, Sigasi added a linting check. When the file encoding differs, Sigasi now report a warning.

 

include_encoding_warning

 

New graphics engine

Sigasi Studio 4.6 contains a new graphics engine, which supports 4K displays and allows Sigasi to add more features in the future. The Block Diagram and State Machines Views already use the new engine. The Dependencies View still uses the old engine. 

Let Sigasi know if you run into any problems. On Linux, make sure webkitgtk is installed. If you use Wayland instead of X11, you might need to set the environment variable WEBKIT_DISABLE_COMPOSITING_MODE=1 .

 

Dependencies View

The analysis behind the Dependencies View was optimised for speed and memory usage. Big projects are now visualised a lot faster, without saturating the memory.

 

 

Other New and Noteworthy Changes

  • Sigasi improved the error messages of the VHDL parser when the code contains empty lists or trailing list separators:

 

vhdl_parser_recovery

 

Sigasi recorded a new screencast on the improved parser.

 

  • Sigasi added support for Fenced Code blocks in comments. This enables you to add text to the documentation without Markdown rendering. To add a comment verbatim to the documentation, surround it with triple back ticks: ```<verbatim comment>``

 

fenced_code_blocks_comment

 

  • Sigasi added a nicer Welcome to Sigasi page
  • Added .vht as supported VHDL file extension
  • The Riviera Pro tool chain now uses the -sv2k9 flag when compiling SystemVerilog files.
  • Signal declaration Quick Fix: Better support for records in port maps
  • The default stack size was increased to 4 MB (for analysing deeply nested statements)
  • Improved the editor’s behaviour when typing the closing quote in a string. It has now the same behaviour as typing the closing parenthesis in a parenthesis pair.
  • We updated upstream Sigasi Studio dependencies:
  • VUnit improvements:
    • Support Python3 on Windows
    • A project clean no longer pops up the VUnit console
    • Rerunning VUnit tests now detects new tests
    • Running all VUnit tests now shows the correct test count

 

Bugfixes 

  • [(System)Verilog] Copy constructor
  • [(System)Verilog] Unexpected indentation of interface classes
  • [(System)Verilog] Ternary operator is not parsed properly in Verilog
  • [(System)Verilog] Verilog parser cannot handle block declaration in module
  • [(System)Verilog] SystemVerilog parse error with inside
  • [(System)Verilog] SV extern method parsing failure
  • [(System)Verilog] SystemVerilog for loops with optional parts fail to parse
  • [(System)Verilog] Inconsistent Verilog formatting in if statements
  • [VHDL] Quick Fix for signal declaration puts signal declaration outside the declarative region
  • [VHDL 2008] Unexpected linking error in external names
  • Sort outline case-insensitive
  • Block Diagram should update while minimised
  • [(System)Verilog] Missing files in toplevel_order.csv export
  • [VHDL] error in compare view
  • [VHDL] Sensitivity list Quick Fix fails on missing sensitivity lists
  • [VHDL] Quick Fix for package body name adds incorrect library name

 

System requirements

  • Sigasi Studio Standalone is supported on:
    • Windows: Windows 10 (64 bit) or newer
    • macOS 10.14 Mojave
    • Linux: RedHat Enterprise Linux RHEL 7.5 (64 bit) or newer
    • More information on supported OSes can be found on the Eclipse website
  • Sigasi Studio as Plugin in your own Eclipse installation:
    • Eclipse 4.7.3a Oxygen up to Eclipse IDE 2019-03
    • Java JRE 8 or higher

We recommend at least 4GB of memory available for Sigasi Studio, and you need about 300MB of free disk space.