Essential VHDL Verification - 14-16 October 2019 Bracknell, UK
3-Day Instructor Led Training
You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).
Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.
Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM.
Core topics include transaction level modelling (TLM), data structures (linked-lists, scoreboards, memories), test generation methods (directed, algorithmic, constrained random and intelligent testbench), self-checking and functional coverage.
- Use OSVVM’s structure transaction base framework
- Write OSVVM Verification IP
- Simplify test writing using interface transactions (CpuRead, CpuWrite)
- Add error injection to interface transactions
- Implement a test plan that maximizes reuse from RTL to core to system-level tests
- Write directed, algorithmic, constrained random, and Intelligent Coverage random tests
- Write Functional Coverage to track your test requirements (test plan)
- Simplify error reporting using OSVVM’s Alert and Affirm utilities
- Simplify conditional message printing (such as for debug) using OSVVM’s log utilities
- Add self-checking to tests
- Use OSVVM’s Generic Scoreboards and FIFOs
- Use OSVVM’s Synchronization Utilities (WaitForBarrier, WaitForClock, …),
- Model analog values and periodic waveforms,
- Utilize OSVVM’s growing library of Open Source Verification IP
To ensure in-depth learning, 50% of the class time is devoted to hands on exercises and labs. The lecture and labs contain numerous examples that can be used as templates to accelerate your test and testbench development.
Delegates should have a good working knowledge of digital circuits and prior exposure to VHDL, either through work or through a previous course.
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