Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).
Riviera-PRO is a high performance, high capacity, multi-language simulator that provides a unified debug environment for VHDL, Verilog, SystemVerilog, SystemC and PSL. The core simulation engine includes advanced simulation optimisation for both VHDL & Verilog simulation.
As well as supporting traditional HDL verification techniques, Riviera-PRO provides advanced analysis and debug capabilities for UVM and TLM verification methodologies.
Riviera-PRO is an extremely capable EDA solution, with all the features that you would expect to see on a high-end verification tool.
Features and Benefits
High Performance Simulation
Industry's Best ROI
FirstEDA is extremely familiar with Riviera-PRO. We have considerable hands-on experience having supported users – verifying FPGA, ASIC and SoC designs – for several years. Working with our customers we have experience of deploying Riviera-PRO on leading-edge FPGA programmes, using advance VHDL techniques such as OSVVM functional coverage and SystemVerilog UVM constrained random tests.
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Ian Gibbins, Applications Specialist, FirstEDA
"With increasing FPGA complexity comes the demand for high performance simulation and verification tools. Our users tell us that Riviera-PRO meets this complexity demand, with extensive language support including VHDL-2018, support for the latest verification libraries (including OSVVM and UVM) and advanced debugging tools. In addition they are finding that the extensive coverage capabilities for fast metric-based verification closure, scripting and batch processing along with the high performance common kernel simulation engine, is providing a solution to meet their performance and verification needs."
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