IDesignSpec

UVM REGISTER MODEL GENERATOR, SYSTEMRDL COMPILER / ASIC D&V

IDesignSpec helps IP/SoC Design architects and engineers to create an executable specification for registers and automatically generate output for Software and Hardware teams.

 

The Agnisys IDesignSpec suite offers your product teams a closely linked set of products, including a unified graphical design interface (GDI) frontend and a unified generation engine. These can be shared across all teams to maximise efficiency and support fully automated flows.

IDesignSpec Suite

IDesignSpec is an end-to-end solution for design and verification of all SoC addressable registers and interrupts, enabling design, verification, firmware and tech pub teams to collaborate from a single specification.

  • Describe registers in Word, Excel, Calc, SystemRDL, IP-XACT, CSV or YAML
  • Auto-generate sign-off quality register RTL code, UVM models, C/C++ headers and documentation
  • Supports various standard bus: AXI4, AXI-Lite, AHB, APB, Wishbone or proprietary

IDesignSpec is a great tool that bridges the gap of register specifications to the design and verification of the actual logic.

Features and Benefits

icons8-facebook-like-64 Automatically verify all addressable registers in the design to ensure generated register code is correct
icons8-synchronize-filled-50 Create synthesisable code for registers for design teams and keep them synchronised with requirements

icons8-fast-forward-50

 

 Faster and more accurate Device Driver, Firmware and application software development eliminates errors in communication of interfaces between functional teams

icons8-database-import-50

 

 Imports : IP-xact, SystemRDL, XML, CSV, register data stored in native editor format. Provides complete register data portability with design teams and customers
icons8-documents-50 Automatically create product documentation for customers and technical publications
icons8-finish-flag-48 Improves productivity of engineers and quality of results
icons8-business-group-80 Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation teams
icons8-delivered-box-64 Extensible: User defined transformations using Tcl or XSLT

IDesignSpec GDI

 

IDesignSpec GDI automates the design and verification of all the memories, register sets, registers, and register fields in your design. You can choose from a variety of input formats or use the highly intuitive specialised editor contained in IDesignSpec GDI. This executable specification supports simple registers as well as many special register types such as indirect, indexed, read-only /write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, and read/write pairs.

From the specifications, IDesignSpec GDI generates a complete RTL design description for the registers and memories, including a bus slave and decode logic specific to the user-selected bus protocol and any clock-domain-crossing (CDC) synchronization logic needed. IDesignSpec GDI also generates a SystemVerilog model compatible with the UVM standard, C/C++ headers for embedded programming, and high-quality documentation suitable for inclusion in user manuals.

IDesignSpec GDI
IDS-Batch CLI

IDS-Batch CLI

 

IDS-Batch CLI runs in command-line mode and generates a wide variety of different output files for the teams on your project, supporting design, verification, embedded programming, validation, and documentation.

IDS-Batch CLI fits seamlessly into your SoC or IP development flow, including integration with the Git revision control system to manage both text and graphics files while fostering collaboration.

From your specifications, IDS-Batch CLI generates output files for your design, verification, software, and documentation teams. It generates the complete RTL description for your registers and memories, including a bus slave and decode logic specific to your selected bus protocol and any clock-domain-crossing (CDC) synchronization logic needed. This enables instant connection of your design to the register bus. Support interfaces include APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, Wishbone, and proprietary buses.

Optional Applications

IDS-Verify

 

The UVM models and C/C++ headers generated by IDesignSpec GDI and IDS-Batch CLI define the register interface through which software monitors and controls the hardware design. Your verification engineers must obtains or develop the UVM sequences necessary to configure, program, and test the registers and memories in the design. Embedded programmers must obtain or write the C/C++ code to perform similar functions for system validation and for production use of the SoC or IP block in the field.

If your verification and software teams manually write sequences in their respective formats, they waste time and resources. There is a high likelihood of differing interpretations and the challenge of keeping the two teams in sync every time the specification changes.

IDS-Verify enables you to describe the custom configuration, programming, and test sequences of your design and automatically generate sequences ready to use during your RTL simulation. From a single sequence specification, IDS-Verify generates UVM sequences for verification and associated documentation. You specify the sequences using a rich language and command feature set that includes loops, branch, wait, calls, switch, and macros.

IDS-Verify
IDS-Validate

IDS-Validate

 

The register verification capabilities of IDS-Verify are extended to your pre-silicon and post-silicon validation by IDS-Validate. IDS-Validate automatically generates both UVM and C/C++ sequences, including specified custom sequences, that exhaustively test your memories and registers. IDS-Validate also extends beyond registers and memories to generate verification environments and user-defined functional tests to verify the functional behavior of your custom design blocks.

IDS-Validate is the solution for SOC/IP teams who aim to cut down the verification your validation time. The automatic generation of UVM and sequences enables exhaustive testing of memories and register maps.

IDS-Validate also provides a way to generate custom tests for your boards as well as UVM and UVM-C based environments through a common specification. This provides a solution for your firmware engineers to write and debug their device drivers and application software.

IDS-Integrate

 

Manually hooking up hundreds or thousands of blocks into a top-level SoC design is a tedious and error-prone process. Many similarly named signals must be connected, with typographical errors certain to occur. The step-and-repeat hookup of repeated instantiations of the same block is especially tedious. Detecting interconnection errors occurs rather late in the project, only when full-chip simulation is ready. Runs are slow and memory intensive at this level, and debug is challenging given the enormous size of the design.

Agnisys has a solution to apply specification automation to SoC-level assembly and interconnection. IDS-Integrate provides a flexible and customisable environment to meet the design requirements for your complete chip.

IDS-Integrate not only interconnects blocks, but it also generates RTL components such as bus multiplexers, aggregators, bridges (AHB to APB, AXI to APB, and AXI4-Full to AHB-Full), and other “plumbing” components as needed. As expected, IDS-Integrate fully comprehends the register RTL designs generated by IDesignSpec GDI and the IP blocks generated by IDS-IPGen.

IDS-Integrate
IDS-IPGen

IDS-IPGen

 

A typical SoC contains hundreds or thousands of RTL blocks from a variety of sources. Many chip companies maintain in-house libraries for commonly used design structures and interfaces. In addition, nearly all SoC projects also license IP blocks from partner companies or commercial IP providers, especially for blocks that implement a standard function such as AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPI, Timer, or UART.

Leveraging IP and reusing parts of previous designs can save your SoC project team a huge amount of time and effort. The downside of using fixed IP blocks is that you may not be able to get exactly what they want. It may be possible to modify and customise IP, but this incurs the risk of breaking the standard functionality. Agnisys IDS-IPGen solves this problem by automatically generating IP blocks from specifications that are highly configurable and customizable.

IDS-IPGen supports a wide variety of standard IP blocks as well as the specification of finite state machines (FSMs), data paths, signals, and other parts of your custom IP blocks. For both standard and custom blocks, IDS-IPGen generates RTL models, UVM verification models, and tests that provide high functional and code coverage right out-of-the-box.

Register Design Entry
Equipped with user-friendly templates, you can specify your registers using any of the add-ins to Word, Excel, OpenOffice Calc or FrameMaker. Built with high-performance IP-XACT compiler and SystemRDL compiler, simple and complex registers can be created hierarchically such that large SoC designs are divided into manageable sub-blocks that are represented symbolically, designed and connected together. This methodology enables you to work on different parts of the design in parallel with a large team. Users are able to convert register spec from IP-XACT to UVM or from SystemRDL to IP-XACT.

Code Generation
Based on the golden specification, various SoC teams can use the high-performance code generators via GUI or command line. The generated RTL Code (VHDL, Verilog, SystemVerilog or SystemC) for the registers is human-readable with easy-to-follow comments. The RTL also includes a bus slave and a decode logic specific to the bus protocol (AHB, APB, AXI, AXI-Lite, or proprietary), ensuring instant connection of the application logic to the register bus. The UVM Register Model Generater generates UVM verification model with Register Arrays, Memories, Indirect Access Registers, FIFO Registers and Coverage, Constraints Models and hdl_path. Users are able to customise various outputs by using our popular Velocity Template and TCL API, enabling you to meet various requirements for RTL, C++ Classes, verification code and documentation.

Special Registers
The UVM library includes examples of few commonly used special registers such as Indirect, Indexed, Alias and RO/WO Registers. But today’s SoCs demand more specialised register behaviour to meet various HW/SW interface requirements. IDesignSpec supports over 20 special registers including Shadow, Lock, Trigger-Buffer, Interrupt, Counter or External.

Document Generation
The customisable Document Generator can output file formats such as HTML, PDF, Custom PDF, .doc, .xls, DITA, IP-XACT, SystemRDL or ARM CMSIS.

 

Advanced UVM Code Generator with SystemRDL to IP-XACT and IP-XACT to UVM Functionalities

What is IP-XACT?

An Accellera standard that provides EDA vendors, IP providers, and SoC design communities with a well-defined and unified specification for the meta-data that represents the components and designs within an electronic system. IDesignSpec includes an IP-XACT Compiler that is able to parse IP-XACT files and output RTL, C Headers and documentation, and supports IP-XACT to UVM verification model conversion.

What is SystemRDL?

Another Accellera standard that supports the full project cycle of registers from the specification, model generation, and design verification to maintenance and documentation. SystemRDL minimises the problems encountered in describing and managing registers. IDesignSpec includes a SystemRDL Compiler that is able to parse SystemRDL files and output RTL, C Headers and documentation, and supports SystemRDL to IP-XACT conversion.

IDesignSpec Availability

IDesignSpec is available as s a plug-in for popular editors that are commonly used to document registers (Microsoft Word, Microsoft Excel) and as a command line utility for Windows, Linux and Solaris platforms. IDesignSpec has three licensing options, Node Locked, Floating Network License and WAN licensing.

Advanced UVM Code Generator

Based on the register definition in IP-XACT or SystemRDL (also Word, Excel or YAML), the UVM Code Generator is able to generate a comprehensive UVM register model with an instance of a register block, files, arrays and memories. Users are also able to define the required coverage type for fields, bits and address-map, and the UVM code generator is able to generate the coverage code for all the components inside the top level block. Customising the code is simple to do by using several UVM properties such as hdl_path, uvm_add_regmap, uvm_backdoor/frontdoor – the UVM code generator will generate the UVM code based on the properties.

 

Related Articles, Blogs and Videos

BLOG: Security Design Strategies in IDesignSpec

BLOG: Register Automation Using Machine Learning

BLOG: RISC-V TileLink Bus Protocol Support in IDesignSpec

BLOG: Creating Test Sequences for RISC-V Cores and SoCs

ARTICLE: IDEX Biometrics Selects Agnisys IDesignSpec to Aid Development of the Next-Generation ASICs for IoT Security

VIDEO: IDesignSpec: Executable Register Specification

VIDEO: Verifying Registers using UVM and IDesignSpec

 

 

  David Clift, Applications Specialist, FirstEDA

“It is vitally important that design teams have a consistent methodology for managing the register map data of their designs. iDesignSpec allows design teams to have a central definition of the memory map of their design, be this in Microsoft Word or Excel format, or industry standard formats such as SystemRDL or IP-XACT. Once this is validated by the tool, they can generate consistent HDL code, documentation, C/C++ headers and more.”

Contact us for more information and pricing.