Agnisys

REGISTER MANAGEMENT AND AUTOMATION

FPGA / ASIC / D&V


Agnisys Inc. is a leading supplier of EDA software for solving complex design and verification problems for system development. Their products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) enabling faster design, verification, firmware, and validation.

Founded in 2007, Agnisys is based in Boston, Massachusetts, with R&D centres in the United States and India. They are a privately held company whose mission is to create automation products that start with a formal specification to deliver design and verification for IPs, Chips & Systems.

Agnisys' strategy is to stay competitive with a focus on creating innovative software solutions to increase the efficiency & work quality of individuals & teams, of System Design & Verification process while achieving their corporate goals.

Development Methodology: Their teams follow proven, standards-based development methodologies for software development, bug tracking, and project management.


FirstEDA is proud to be the sole distribution and support channel for Agnisys in the UK, Ireland, France, Belgium, The Netherlands, Spain, Portugal and across the Nordic countries.

Products

 

 

IDesignSpec

 

IDesignSpec enables IP, SoC, FPGA & ASIC teams to standardise on the register specification and generate Verilog, VHDL, UVM, C headers, Word, Excel, PDF, and many other formats from it. IDesignSpec is currently available in Word, Excel, and as a Batch utility.

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ISequenceSpec

 

ISequenceSpec creates Portable Register based sequences and generates UVM and Firmware sequences from the register specification. It uses the register information by importing the standard formats like IP-XACT, SystemRDL, and any IDS format.

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IDS NextGen

 

IDS NextGen helps users to create SoC specifications at an enterprise level. It handles individual IP to sub-system to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV and System RDL. IDS NextGen generates design and verification code for not just registers, but sequences in one integrated environment. It reduces the verification time by generating the entire UVM SV and SystemC output sequences.

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ARV

 

ARV is an add-on to IDesignSpec that creates a complete verification environment for automatically verifying all addressable registers with all access types and all complex types for IP and SoC. Its a one of a kind tool which saves you verification resources.

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DVinsight-Pro

DVinsight is a smart editor for creating UVM based System Verilog Design and Verification code is now available on Redhat 7, 6 & 5, Ubuntu and Windows. Simplify your SV/UVM coding process with this new editor which you can use for free.

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Media

 

Webinars

Agnisys schedule regular live webinars covering wide variety of topics; From technology and best practices that IP/FPGA/ASIC developers will find useful and interesting, to presenting and discussing the latest innovations in their tools and solutions.

All webinars are recorded and available to view on-demand afterwards.

 

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Videos